Hot-carrier effects are known to cause serious performance degradation in short-channel MOS devices which use conventional drain structures. To remedy this problem, alternative drain structures such as lightly doped drain (LDD) structures have been developed.
FIGS. 1 through 4 illustrate a typical prior art method for fabricating a transistor using an LDD.
As shown therein, a P type substrate 10 is initially provided, and a thin gate oxide 12 is grown thereover. A polysilicon gate 14 is formed over the thin gate oxide 12 by photoresist and etching steps as is well known. An N- implant is undertaken through the thin gate oxide on either side of the gate 14, and the implanted ions are driven in to form lightly doped regions 16 and 18, which are self-aligned with the edges of the gate 14.
A layer of oxide 20 (FIG. 2) is deposited over the resulting structure. The oxide 20 is anisotropically etched to form spacers 22, 24 on the sides of polysilicon gate 14 (FIG. 3). An anisotropic dry etching process is typically used to form spacers 22, 24 since wet etching processes are usually isotropic and generally unable to construct spacers having a suitable form.
As also shown in FIG. 3, N+ ions are implanted and driven in (FIG. 4) to form heavily doped regions 26, 28 which are self aligned with the edges of the spacers 22, 24.
The form of the LDD region 18A, which determines the hot carrier performance of the device, is established by the spacer profile. The spacer profile varies as a function of the oxide 20 etch time and the oxide 20 thickness. A particular amount of over-etch is necessary to form the spacers 22, 24, however, excessive over-etching reduces the width and height of the spacers 22, 24 and causes gouging into the silicon 10 by etching through the thin oxide 12 on the sides of the gate 14 and exposing the silicon 10 to the etchant. Control of this over-etch process becomes more difficult as the deposited oxide layer 20 thickness increases.
Additionally, the use of such a process results in a lightly doped drain region 18A having a form determined by the spacer profile. It may well be advantageous to provide a more refined spacer profile to enhance performance of the device, with it also being understood that the process for achieving this should be simple and effective.